Patents & IP

See patent application filed

The ASIC UltraBoost is an improvement of the Bitcoin mining process, building on all other existing optimisations in the market, including ASIC Boost, achieved by eliminating redundant computation of a key part of the Bitcoin mining algorithm, resulting in a faster and more efficient mining process.

The optimisation starts from the initial consideration that currently, Bitcoin miners attempt to find the winning hash acceptable to the Bitcoin Network by calculating multiple midstates (by rolling the Version), passing them through further hashing (by rolling the Nonce) to obtain a final hash value that is less than or equal to the Target.

ASIC UltraBoost looks to improve the algorithmic efficiency of Bitcoin mining by proposing 3 specific variants to the SHA256 message scheduler for the 3 instances of SHA256 in Bitcoin mining. These Optimal SHA256 Message Schedule Variants result in faster and more efficient Bitcoin mining by eliminating the redundant computations within the SHA256 message schedule specific to Bitcoin mining. As such, the calculation of the midstates alongside the calculation of the message digest is significantly optimised. ASIC UltraBoost reduces the Message Schedule calculations for the 3 iterations of SHA256 by approximately 20%, as follows:

The SHA256 function being a combination of the message schedule and the compression function, when considering the optimisations of ASIC UltraBoost for the entire SHA256 function, the number of operations across the 3 iterations of SHA256 are reduced by approximately 7%.

More accurate results, including an overall percentage improvement, will be available when ASIC UltraBoost is implemented in hardware.

ASIC EnhancedBoost is an innovative approach to SHA-256 optimised computation for Bitcoin mining. This novel approach, called Message Scheduling For Cryptographic Hashing (“MSFCA”), addresses one of the most challenging problems in BTC mining: partial pre-computing of future blockchains’ blocks.

The computational optimisation obtained by MSFCA allows, under BTC mining special conditions, the miner to asynchronously perform (i.e. not within the temporal boundaries of the current block being computed) partial pre-computations of future blocks, before the ten minute computation ‘time target’ for closing a new block begins. The benefit being that all the logical gates and computation time on the ASIC chip needed for the specific partial pre-computation are saved.

This is novel procedure is potentially capable, in certain conditions, of addressing a key BTC mining limitation that prevents asynchronous pre-computation of a new block in the blockchain prior to the previous block being closed. Application of MSFCA is not believed to enhance SHA-256’s computation performance time; however, by enabling partial SHA-256 pre-processing of the block, it makes it possible to save the hardware resources otherwise necessary for standard SHA-256 computation. From this perspective, it is anticipated that energy would be saved due to less logic gates being present on the ASIC allowing the same chip area to be used to implement additional SHA-256 engines and increasing the overall speed of the process.

The key principle of this approach is that the partial pre-computation can occur asynchronously. Implementation of MSFCA will require a specific ASIC architecture, hence a specific ASIC chip will need to be designed, however the Company believes this would only require a feasible modification of the current SHA256 proprietary implementation being developed by QBT.

In terms of SHA-256 ASIC chip areas, the projected potential saving would be in the region of 25% for one instance of SHA256 out of the three instances involved in Bitcoin mining. However, because of other well-known optimisation techniques, the effective potential area saving of MSFCA is estimated by the Company’s ASIC designer to be around 8% on average.

The handling of pre-processed data requires additional circuitry, the impact of which is expected to be negligible in the near future. While MSFCA can be implemented with currently available technology, by adding a logical gate overhead, in the near future, the Company believes these overheads will be less relevant, making this approach even more competitive. Despite present technological limitations, (for example, the limited throughput of memory chips), the Company believes that it is strategically important to file a patent application covering the novel approach created through the use of MSFCA.